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<h1 class="page">随机存取存储器（RAM）实验</h1>
<div class="sect1">
<h2 id="_实验目的"><a class="anchor" href="#_实验目的"></a>实验目的</h2>
<div class="sectionbody">
<div class="olist arabic">
<ol class="arabic">
<li>
<p>熟悉RAM的功能特性及用法。</p>
</li>
</ol>
</div>
</div>
</div>
<div class="sect1">
<h2 id="_实验原理"><a class="anchor" href="#_实验原理"></a>实验原理</h2>
<div class="sectionbody">
<div class="paragraph">
<p>RAM（Random Access Memory），即随机存取存储器，通常是指可随机读写任一存储单元的半导体存储器。RAM又分为静态RAM（Static RAM）和动态RAM（Dynamic RAM），本实验针对静态RAM。</p>
</div>
<div class="paragraph">
<p>RAM芯片通常有下列引脚。</p>
</div>
<div class="ulist">
<ul>
<li>
<p>地址（A）：用于指定RAM中将要访问的存储单元的位置。地址位数决定了RAM芯片的地址范围，m位地址（A<sub>m-1</sub>～A<sub>0</sub>）的寻址范围为0～2<sup>m</sup>-1；例如，4位地址意味着RAM模块有16个单元，地址为0～15。</p>
</li>
<li>
<p>数据输入（DI）和数据输出（DO）：写入操作时数据通过DI引脚输入到RAM，读取操作时数据从RAM输出到DO引脚。DI和DO引脚的位数是相同的，决定了每次访问可以传输的数据位数；对于静态RAM，通常与字长一致，即n位的数据引脚D<sub>n-1</sub>～D<sub>0</sub>意味着SRAM的字长为n。有些RAM芯片的数据输入和数据输出引脚是复合的。</p>
</li>
<li>
<p>写使能（WE）：控制是否允许写入操作。有效时允许数据写入，无效时禁止写入。</p>
</li>
<li>
<p>输出使能（OE）：控制是否允许数据输出。有效时允许数据从RAM输出，无效时数据输出引脚处于高阻态。</p>
</li>
<li>
<p>芯片使能（CE或CS）：用于控制RAM芯片的工作状态。有效时芯片被选中，可以进行读写；无效时芯片处于非激活状态，禁止芯片读写。如果用多个RAM芯片组成一个更大容量的存储器，该引脚起到关键作用。</p>
</li>
<li>
<p>时钟引脚（CLK）：同步型RAM芯片会有时钟引脚，其用法取决于芯片设计。</p>
</li>
</ul>
</div>
<div class="admonitionblock note">
<table>
<tr>
<td class="icon">
<i class="fa icon-note" title="注"></i>
</td>
<td class="content">
<div class="dlist">
<dl>
<dt class="hdlist1">有效电平</dt>
<dd>
<p>上面WE、OE和CE引脚都提到了“有效”，但并未说明是高电平有效、还是低电平有效。对于物理RAM芯片引脚通常是低电平有效，但芯片内部逻辑一般是高电平有效。Digital仿真软件采用高电平有效。</p>
</dd>
</dl>
</div>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="sect1">
<h2 id="_实验任务"><a class="anchor" href="#_实验任务"></a>实验任务</h2>
<div class="sectionbody">
<div class="sect2">
<h3 id="_设计任务"><a class="anchor" href="#_设计任务"></a>设计任务</h3>
<div class="paragraph">
<p>设计RAM组件的验证电路。
RAM组件位于菜单项「组件 ➤ 存储器 ➤ RAM ➤ RAM(独立端口)」（Components ➤ Memory ➤ RAM ➤ RAM, separated Ports）。
RAM组件的属性设置为：数据位数：8；地址位数：4。
RAM组件端口名称与实验原理中常规RAM芯片引脚名称的对应如<a href="#tab-mem-ram-1">表 1</a>所示。</p>
</div>
<table id="tab-mem-ram-1" class="tableblock frame-all grid-all stretch">
<caption class="title">表 1. 端口名称对照</caption>
<colgroup>
<col style="width: 21%;">
<col style="width: 21%;">
<col style="width: 58%;">
</colgroup>
<thead>
<tr>
<th class="tableblock halign-center valign-top">实验原理的引脚名称</th>
<th class="tableblock halign-center valign-top">RAM组件端口名称</th>
<th class="tableblock halign-left valign-top">备注</th>
</tr>
</thead>
<tbody>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">A</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">A</p></td>
<td class="tableblock halign-left valign-top"></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">DI</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">Din</p></td>
<td class="tableblock halign-left valign-top"></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">DO</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">D</p></td>
<td class="tableblock halign-left valign-top"></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">WE</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">str</p></td>
<td class="tableblock halign-left valign-middle" rowspan="2"><p class="tableblock">RAM组件读写控制端口的名称可能有些令人费解。str、ld对应的单词分别是store和load，将来学习了控制器实验的<a href="cu-overview.html#bookmark-cu-isa" class="xref page">指令系统</a>之后，也许能够理解这样命名的原因。</p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">OE</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">ld</p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">CE/CS</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">-</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">本实验所用RAM组件无此端口。</p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock">CLK</p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock">C</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">RAM组件写入需时钟同步，但读出无需时钟。</p></td>
</tr>
</tbody>
</table>
<div class="paragraph">
<p>将RAM组件的所有端口分别连接到输入、输出组件。注意端口C应连接时钟输入组件，连接地址、数据端口的输入、输出组件的数据位数应与地址、数据端口的数据位数一致。</p>
</div>
</div>
<div class="sect2">
<h3 id="_验证任务"><a class="anchor" href="#_验证任务"></a>验证任务</h3>
<div class="paragraph">
<p>通过仿真向不同的RAM单元写入不同的数据然后读出验证。
熟悉RAM的功能、用法，记录仿真过程并保存数据。</p>
</div>
<div class="dlist">
<dl>
<dt class="hdlist1">思考</dt>
<dd>
<p>RAM组件的读写方法与双端口寄存器堆的读写方法有何异同？</p>
</dd>
</dl>
</div>
<div class="sidebarblock text-center">
<div class="content">
<div class="title">许可 | License</div>
<div class="paragraph">
<p><a href="https://creativecommons.org/licenses/by-nc-sa/4.0/deed.zh">CC BY-NC-SA：署名-非商业性使用-相同方式共享 4.0 国际许可协议</a></p>
</div>
<div class="paragraph">
<p>作者：
肖铁军 &lt;<a href="mailto:xiaotiejun@foxmail.com.cn">xiaotiejun@foxmail.com.cn</a>&gt;</p>
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